The Path to Useful Quantum Computing Needs a QEC Roadmap

Let’s unpack each of these steps.

The good news is that we’ve already achieved this first step: Creating a decoder that enables quantum-memory demonstrations which unlock the first real-time feature, deterministic decoding.

For this, a QEC code—the Surface Code—is widely regarded as the leader of the QEC pack. It’s also the code that the Google and Zurich teams used in their demonstrations.    

But other potential codes could steal the Surface Code’s QEC crown.

At Riverlane, for example, we developed the Collision Clustering algorithm, which works by growing clusters of errors and quickly evaluating whether they collide or not. This code not only provides a speed advantage, but also balances the speed, accuracy, cost, hardware, and power requirements to provide a practical route to error-corrected quantum computing.      

To implement Collision Clustering, we coded in Verilog, which enables it to load onto an FPGA. While lots of excellent software packages are available for decoding, they’re coded in higher-level languages suitable for CPUs and aren’t necessarily going to behave deterministically.   

FPGAs are a useful platform as every quantum computer in the world currently uses them to generate pulses to control qubits. So, this means the decoder can easily slot in alongside existing infrastructures.

Indeed, you could use such a decoder for up to 1,000 qubits and it would still consume less than 6% of the resources on an FPGA (based on a Xilinx). It could even share space with an FPGA without needing any new hardware purchases.  

In the longer term, the cost and bulk of FPGAs means that large quantum computers will need to shift to using application-specific integration circuits (ASICs) for their decoders and control systems. An ASIC looks a lot like the CPU inside your laptop or phone, but it’s tailored for a specific task and behaves more deterministically like an FPGA.   

Compared to an FPGA, an ASIC is faster, much cheaper (pennies per unit rather than tens of thousands of pounds), and much lower in power consumption. The catch is that building an ASIC requires a foundry to tapeout your design onto a silicon chip. Every new generation or update to your decoder needs a new tapeout.  So, they aren’t as quickly deployable since most current quantum computers use FPGAs for their control systems.    

In summary, FPGAs are convenient now, but ASICs are the future.

What Next?

Riverlane’s current decoder takes the output of a whole QEC experiment (including preparing the logical qubit and finally reading it out) and decodes it as a single batch of all syndrome data generated by that experiment (Fig. 2). It completes this task quickly and in a reliable amount of time (the decoder behaves deterministically). But it isn’t continuously decoding a stream of data.

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