Accelerating Time-to-Market: The Impact of Shift Left Verification on IC Design Productivity

The process of design iteration and eventual production of an integrated circuit (IC) chip is traditionally a “shift right” activity, with errors and missed optimization opportunities in early design stages tending to cascade into multiple signoff verification iterations. This approach can push project completion and time to market further into the future than is intended or desirable, as design teams spend critical cycles correcting and adjusting layouts during signoff to achieve tapeout.

The “shift left” concept in software development encourages earlier resolution of software bugs. In IC design, shift left means finding and fixing errors when design layouts are more accessible. The Calibre® nmPlatform introduces foundry-trusted signoff-quality analysis/verification/optimization into earlier design stages, using innovative tools and technologies to reduce timelines, minimize errors during signoff, ensure more efficient use of time and resources, and produce faster times to market. By proactively analyzing layouts and detecting critical problems earlier in the design flow, Calibre shift left analysis/verification/optimization benefits every team, individual team member, and the enterprise as a whole.

Of course, different designs have different verification needs. To ensure full benefit is achieved from implementing a shift left verification strategy, all designers must understand how to integrate Calibre design-stage verification within their existing design and implementation processes, and which features of Calibre verification best suit their particular requirements. Knowing why and how to optimize a shift left verification implementation can help design teams ensure the process shift takes place smoothly and efficiently, so companies and designers alike can benefit from the improved productivity and design quality sooner.

Like anything new, the compelling value proposition of the Calibre shift left verification strategy can be obscured by uncertainty regarding how it can best be implemented. Fortunately, the principals are straightforward.

A brief overview of design-stage verification implementation by key process
Calibre shift left design-stage verification from Siemens EDA incorporates four key components, from which further specifics naturally flow.

 Verification: Implementing Calibre verification earlier in the design flow not only enables targeted design and reliability issues to be detected and fixed with signoff quality in early design stages, but also provides design teams with the full range of Calibre verification capabilities. By relying on qualified Calibre rule decks and proven high-performance engines, Calibre design-stage verification applies traditional verification such as design rule checking (DRC), layout versus schematic (LVS) verification, and circuit verification, as well as embracing expanding verification needs such as power, thermal, and stress analysis, and multigon curvilinear layout construct verification. Fixes applied early in implementation will remain Calibre-clean throughout signoff, reducing tapeout iterations and unpleasant last-minute surprises. Designers can use innovative Calibre shift left verification tools and functionalities for verifying all types of designs, from intellectual property (IP) to block and full chip layouts, to 2.5D and 3D stacked packages.
Execution: Intelligent heuristics and models are critical to the efficient and accurate execution of Calibre design-stage verification. Innovative paradigms select and focus verification activities on critical early-stage issues, while a user-friendly environment supports designers at the point of use and integrates seamlessly with familiar design and implementation tools.
Debug: Sharply focused and automated debug strategies and technologies make Calibre analysis and resolution of design errors simpler and faster. Calibre is the industry leader in debug tools and technologies that support fast, accurate debugging. The Calibre nmPlatform continues to expand capabilities using new AI techniques for result clustering, making it easier to debug common design errors that would ordinarily be time-consuming to find and fix. By associating such errors to root cause categories, the Calibre debug process identifies violation clusters likely to share a common origin or root cause, enabling designers to analyze and fix the layout more quickly and accurately.
 Layout optimization: Layout optimization capabilities are a familiar part of design implementation tools, but the full-featured Calibre shift left strategy incorporates selective design-stage layout optimizations using Calibre’s layout processing engine for improved performance, quality, and productivity. Calibre automated layout optimization functions deliver meaningfully faster and more reliable performance, and remain Calibre signoff-compliant through tapeout. Applying Calibre-clean selective optimizations in early design stages leads to significantly reduced rework during chip finishing and higher reliability designs.

Understanding how shift left design-stage verification benefits designers
Calibre design-stage verification impacts all types of IC design engineers in many positive ways by enabling design-stage signoff-quality analysis/verification/enhancement that can be focused on specific needs and requirements. The ability to use a single, foundry-trusted toolsuite from early design stages through signoff verification ensures design rules are checked and errors are corrected consistently with signoff-level quality at every stage of the design flow.

Hard IP often consists of custom designs that have been validated as accurate running Calibre using sign-off PDK decks.  IP is often reused in multiple designs after being silicon certified and it can be critical to confirm that when reused in subsequent designs that nothing has changed in the IP.  Determining nothing has changed can be challenging without using advanced Calibre pattern matching technology. Calibre design-stage verification can help IP designers by quickly identifying which IP layers and specific polygons have changed to minimize the designer time required to make repairs. Similarly, soft IP (typically SRAM compiled from a library) should always generate a legal layout. However, errors such as very slight misalignments of even 1 nm can result in failures in either performance or yield. Comprehensive checking functionality can be used to quickly detect and correct any misalignments or symmetry issues, no matter how small, in early design stages. Clear guidance for fixing newly identified errors ensures that once these designs reach signoff verification, fixes made in early design stages remain Calibre-compliant throughout tapeout.

Block and full chip designers must manage many concurrent design flows throughout the overall design implementation. IP, blocks, and the top-level layout are all designed simultaneously, which can create an array of verification challenges. During early design and implementation, Calibre design-stage verification automatically focuses only on systemic and critical design issues, disabling checks that would result in transitory errors or excessive runtimes. This selective check analysis is completely node-agnostic and doesn’t rely on switch settings from foundry decks or the manual creation of check groups. High-speed local interactive verification and chip finishing in the place and route (P&R) or design tool cockpit, using qualified Calibre signoff engines, dramatically reduces the number of long loop iterations needed. Not only are time-consuming streamouts and back annotations eliminated, but fixes that pass verification stay Calibre signoff-compliant during subsequent iterations, all the way through tapeout.

Even 2.5DIC and 3DIC designers can benefit from a Calibre shift left verification strategy. By combining Calibre signoff-quality verification with package design tools, assembly designers can quickly analyze and evaluate multiple floorplans. Once a package layout is selected, an assembly description defining the package stackup can be generated. With this description, designers can use the Calibre 3DSTACK tool to run physical verification across the assembly, enabling a single deck and single run to not only identify and display DRC and LVS issues in a single results output, but also generate a post-assembly netlist for further analysis, including reliability analysis, as well as identifying thermal and stress impacts.

Fitting Calibre shift left verification into teams and processes
The Calibre shift left strategy can be a true game-changer in other ways. Instead of requiring P&R engineers and designers to learn elaborate setup configurations and invocation procedures, user-friendly interfaces and processes simplify the Calibre run process. Once designers specify their current position in a design flow and their ultimate business goals, built-in intelligence can determine optimal setup, check selection, and hardware requirements. This intelligent shift left approach means organizations can simultaneously improve the efficiency of their software and hardware resources while helping designers and engineers accomplish more faster.

Seizing the benefits of shift left to help each stakeholder perform better and boost enterprise-wide results
Calibre design-stage verification can largely eliminate critical and systemic errors early in the design flow, eliminate these problems once upstream during design implementation avoiding last minute surprises at tapeout helping teams meet tight tapeout schedules while ensuring optimal design efficiency, performance, reliability, and yield. With dedicated Calibre tools, designers across the IC design and implementation spectrum can significantly reduce the time and effort needed to complete verification tasks and ultimately deliver value. Faster iteration times, significantly reduced manual review and debug times, Calibre-clean design optimizations, and reduced overall iterations translate to increased productivity, higher quality designs, and faster time to market.

The art of IC design changes every day. When faced with integrating many large functional blocks and billions of devices assembled with increasing degrees of automation, IC verification needs to keep pace. Today’s best shift left solutions, such as that found in the Siemens Calibre nmPlatform, include innovative tools and functionality that can bring a laser focus and signoff-quality results to early design-stage verification. The Calibre shift left solutions deliver optimal designer productivity, signoff-quality results, and industry-leading runtime performance to enhance every design and verification flow.

Want to learn more about Calibre shift left solutions and how they can help your company deliver better designs faster? Visit Calibre Shift Left solutions at Siemens EDA for more details and resources.


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