What’s the Difference Between the Nanosheet FET and FinFET?


So, the standard cells, which are the building blocks of logic libraries, ended up moving from a three-fin device to a dual-fin device. The knob that companies turned to scale the transistors was called “track height scaling.” You could scale the standard cell structurally without scaling the pitches, simply because you could depopulate the number of fins and, instead, use taller and taller fins. So, there are two arguments in favor of the FinFET—one is better electrostatic control, the other is better efficiency.

Then, tell me why the semiconductor industry is trying to replace the FinFET, despite all its advantages. Why is it at the end of its rope?

Let me preface this by saying that although the transition from planar- to fin-shaped transistors was a no-brainer, the nanosheet will unfortunately have a harder time bringing the same benefits that we’ve seen from the FinFET.

The reason we’re moving to nanosheet is mostly because of electrostatic control. You previously used a fin that was anchored into the wafer, and it required the fin to have a very straight profile, so you needed a thin fin of very straight silicon from the top to the bottom—the foot of the fin—to make sure that you have precise control across the channel.

However, the fin profiles are never perfectly straight, so you always have some degree of power leaking from the bottom of the fin. Some of the major foundries are trying to improve the fin profile to guarantee the electrostatic control. But honestly, there’s only so much you can do.

At the same time, everyone wanted to scale the gate length of the transistor, but they realized that it was getting more challenging to keep scaling the fin and the gate length at the same time and still guarantee the same electrostatic control.

What’s happening is we’re moving to a complete GAA structure, where the whole channel is wrapped around on all four sides to get the strong gate field that can guarantee a strong turn on and turn off and reduce leakage current. That way, you can continue to scale the gate length within the nanosheet device.

So, is it simply no longer sustainable to use the FinFET at the scale of the most advanced process nodes? What is the payoff for companies that can figure out nanosheet technology?

Right. The problem is just a matter of geometry. As you manufacture smaller and smaller transistors, you end up with a pair of fins per device. The next step is to explore the possibility of a single-fin device, right? But the problem with a single fin, if you want to maintain the drive current that you had with a pair of fins, is you need to double the height of the single fin.

So, for instance, maybe the fin is 50-nm high in a double-fin scenario. With a single fin, you would have to go to a 100-nm fin, which is very tall and, as a result, very tough to manufacture in a cost-efficient way.

And at the same time, the amount of parasitics [most notably the capacitance and resistance] that you accumulate in such a tall structure would deplete all the advantages of making the device more compact in the first place. So, it’s not as though the 100-nm fin would work as well as a pair of 50-nm fins placed side-by-side.

When we realized that the two-fin device was close to the end of its life, it turned out geometrically chopping the single fin into slabs—for example, 20 to 25 nm tall—and then stacking them on top of each other with the gate wrapping around [the channel] gives you the best compromise in terms of effective width [maximizing drive current] and minimizing parasitics [in the same footprint that would fit a single fin]. It’s just pure geometry.

This is why companies have started investing in the transition to nanosheet transistors, and it is also why you see different foundries taking different trajectories. Some foundries have introduced nanosheet before others, and that is simply because the nanosheet and the FinFET are still competing for dominance at these dimensions—in terms of striking [a balance between] the efficiency, drive, and parasitics of the device.

You’re saying that they are all trying to determine when it is worth it to go through the trouble of transitioning to the nanosheet.

Exactly. We know the separation between the two fins is limited by how much metal you can squeeze between the two fins to form the gate, so at some point you will get stuck with one single fin, and with a single fin, you know you’re toast. You can’t get the same power and performance improvements without the nanosheet. The crossover point depends on your trajectory, but that happens at around 3-nm or 2-nm node dimensions.



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